Partitioning VLSI-Circuits for Parallel Simulation on Transistor Level

For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper we present a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects and balanced subcircuit sizes. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.